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| cy8c20x46, cy8c20x66 capsense? applications cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12696 rev. *c revised october 13, 2008 features low power capsense tm block ? configurable capacitive sensing elements ? supports combination of capsense buttons, sliders, touchpads, touchscreens, and proximity sensors powerful harvard architecture processor ? m8c processor speeds running to 24 mhz ? low power at high speed ? interrupt controller ? 1.71v to 5.5v operating voltage ? temperature range: ? 40c to +85c flexible on-chip memory ? two program storage size options ? cy8c20x46: 16k flash ? cy8c20x66: 32k flash ? 50,000 erase/write cycles ? 2048 bytes sram data storage ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) full-speed usb (12 maps) ? eight uni-directional endpoints ? one bi-directional control endpoint ? usb 2.0 compliant ? dedicated 512 byte buffer ? internal 3.3v output regulator ? available on 48-pin qfn and 48-pin ssop packages only ? operating voltage with usb enabled: ? 3.15 to 3.45v when supply voltage is around 3.3v ? 4.35 to 5.25v when supply voltage is around 5.0v complete development tools ? free development tool (psoc designer?) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 5.0% 6/12/24 mhz main oscillator ? internal low speed oscillator at 32 khz for watchdog and sleep ? optional external 32 khz crystal ? 0.25% accuracy for usb with no external components programmable pin configurations ? 25 ma sink current on all gpio ? pull up, high z, open drain drive modes on all gpio ? cmos drive mode on ports 0 and 1 ? up to 36 analog inputs on gpio ? configurable inputs on all gpio ? selectable, regulated digital io on port 1 ? configurable input threshold for port 1 ? 3.0v, 20 ma total port 1 source current ? 5 ma source current mode on ports 0 and 1 ? hot-swap capability on all port1 gpio versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations ? high psrr comparator ? low dropout voltage regulator for the analog array additional system resources ? i 2 c? slave ? selectable to 50 khz, 100 khz, or 400 khz ? implementation requires no clock stretching ? implementation during sleep modes with less than 100 a ? hardware address detection ? spi? master and spi slave ? configurable between 46.9 khz ? 12 mhz ? three 16-bit timers ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit package options ? 16-pin 3x3 x 0.6 mm qfn ? 24-pin 4x4 x 0.6 mm qfn ? 32-pin 5x5 x 0.6 mm qfn ? 48-pin 7x7 x 1.0 mm qfn (cy8c20x66 only) ? 48-pin ssop [+] feedback
cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 2 of 34 block diagram capsense system 2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 16k/32k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 capsense module global analog interconnect 1.8/2.5/3v ldo analog mux two comparators i2c slave spi master/ slave por and lvd usb system resets internal voltage references three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 3 of 34 psoc ? functional overview the psoc family consists of many mixed-signal array with on- chip controller devices. these devices are designed to replace multiple traditional mcu-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog a nd digital blocks, as well as programmable interconnect. this architecture allows the user to create customized peripheral configurat ions, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memo ry, and configurable io are included in a range of convenient pinouts. the architecture for this device family, as illustrated above, is comprised of three main areas: the core, the capsense analog system, and the system resource s (including a full-speed usb port). a common, versatile bus allows connection between io and the analog system. each cy8c20x46/cy8c20x66 psoc device includes a dedicated capsense block that provides sensing and scanning control circ uitry for capacitive sensing applications. depending on the psoc package, up to 36 general purpose io (gpio) are also included. the gpio provides access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-mips, 8-bit harvard architecture microprocessor. system resources provide additiona l capability, such as config- urable usb and i2c slave/spi master-slave communication interface, three 16-bit progra mmable timers, and various system resets supported by the m8c. the analog system is composed of the capsense psoc block and an internal 1.2v analog re ference, which together support capacitive sensing of up to 36 inputs. capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins are completed quickly and easily across multiple ports. figure 1. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables sele cted pins to precharge continu- ously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: complex capacitive sensing inte rfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any io pin. crosspoint connection between any io pin combinations. when designing capacitive sensing applications, refer to the lat- est signal-to-noise signal level requirements application notes, which can be found under http://www.cypress.com >> docu- mentation >> application notes. in general, and unless other- wise noted in the relevant a pplication notes, the minimum signal-to-noise ratio (snr) for capsense applications is 5:1. idac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select oscillator csclk imo [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 4 of 34 additional system resources system resources, some of which have been previously listed, provide additional ca pability useful to complete systems. additional resources include low voltage detection and power on reset. the merits of each system resource are listed here: the i2c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over 3 or 4 wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). the i2c hardware address recognition feature reduces the already low power consumption by eliminating the need for cpu intervention until a packet addressed to the target device is received. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power-on-reset) circuit elim inates the need for a system supervisor. an internal reference provides an absolute reference for capac- itive sensing. the 5.5v maximum input, 1.8/ 2.5/3v-selectabl e output, low- dropout regulator (ldo) provides regulation for ios. a register- controlled bypass mode allows the user to disable the ldo. standard cypress psoc ide tools are available for debugging the cy8c20x46/cy8c20x66 family of parts. however, the additional trace length and a minimal ground plane in the flex- pod can create noise problems that make it difficult to debug a power psoc design. a custom bonded on-chip debug (ocd) device is available in an 48-pin qfn package. the ocd device is recommended for debugging designs that have high current and/or high analog accuracy requirements. the qfn package is compact and is connected to the ice through a high density connector. getting started the quickest path to understanding the psoc silicon is by reading this data sheet and us ing the psoc designer integrated development environment (ide). th is data sheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc mixed- signal array technical reference manual , which can be found on http://www.cypress.com/psoc . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cyp ress.com/shop/ . under product categories click psoc? mixed signal arrays to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog and capsense. go to http://www.cypress. com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on support located at the top of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reache d with a four hour guaranteed response at http://www.cypress.com/support . application notes a long list of application notes assists you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the documentation list loca ted at the top of the web page. application notes are so rted by date by default. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 5 of 34 development tools psoc designer? is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows xp and windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built-i n support for third-party assem- blers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view the system-level view is a drag-and-drop visual embedded system design environment based on psoc express. in this view you solve design problems the same way you might think about the system. select input and output devices based upon system requirements. add a comm unication interface and define the interface to the system (reg isters). define when and how an output device changes state based upon any/all other system devices. based upon the design , psoc designer automatically selects one or more psoc mixed-signal controllers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer 4.x. you choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. you conf igure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on- chip resources. all views of the project share common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third-party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 6 of 34 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-l evel views provide a library of pre-built, pre-tested hardware peripheral components. in the system-level view these com ponents are called ?drivers? and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for example) , communication interfaces (i 2 c- bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view the components are called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed-signal varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. both the system-level drivers an d chip-level user modules are documented in data sheets that are viewed directly in psoc designer. these data sheets explain the internal operation of the component and provide performance specifications. each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the io pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view select ing a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog-to- digital converter (adc) to conver t the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, you perform the selection, configuration, and routing so that you have comp lete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification a nd provides the software for the system. both system-level and chip-lev el designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the in-circuit emulator (ice) where it runs at full speed. psoc designer debugging capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 7 of 34 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. units of measure lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. table 1. acronyms acronym description ac alternating current api application programming interface cpu central processing unit dc direct current fsr full scale range gpio general purpose io gui graphical user interface ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output lsb least-significant bit lvd low voltage detect msb most-significant bit por power on reset ppor precision power on reset psoc? programmable system-on-chip? slimo slow imo sram static random access memory [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 8 of 34 pin information this section describes, lists, and illu strates the cy8c20x46/cy8c20x66 psoc devi ce pins and pinout configurations. the cy8c20x46/cy8c20x66 psoc device is available in a variety of packages which are listed and ill ustrated in the following tab les. every port pin (labeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, and xr es are not capable of digital io. 16-pin part pinout table 2. 16-pin qfn part pinout (2) pin no. type name description figure 2. cy8c20246, cy8c20266 16-pin psoc device digital analog 1 io i p2[5] crystal output (xout). 2 io i p2[3] crystal input (xin). 3 iohr i p1[7] i2c scl, spi ss. 4 iohr i p1[5] i2c sda, spi miso. 5 iohr i p1[3] spi clk. 6 iohr i p1[1] issp clk (1) , i2c scl, spi mosi. 7 power vss ground connection. 8 iohr i p1[0] issp data (1) , i2c sda, spi clk. 9 iohr i p1[2] 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull down. 12 ioh i p0[4] 13 power vdd supply voltage. 14 ioh i p0[7] 15 ioh i p0[3] integrating input. 16 ioh i p0[1] integrating input. legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn (top view) ai, xout, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4], ai ai, clk 1 , spi mosi, p1[1] ai, data 1 , i2c sda, spi clk, p1[0] p1[2], ai ai, xin, p2[3] p1[4], extclk, ai xres p0[1], ai vss 12 5 6 7 8 notes 1. these are the issp pins, which are not high z at por (power on reset). 2. during power up or reset event, device p1[1] and p1[0] may dist urb the i2c bus. use alternate pins if you encounter any issue s. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 9 of 34 24-pin part pinout table 3. 24-pin qfn part pinout (2, 3) pin no. type name description figure 3. cy8c20346, cy8c20366 24-pin psoc device digital analog 1 io i p2[5] crystal output (xout). 2 io i p2[3] crystal input (xin). 3 io i p2[1] 4 iohr i p1[7] i2c scl, spi ss. 5 iohr i p1[5] i2c sda, spi miso. 6 iohr i p1[3] spi clk. 7 iohr i p1[1] issp clk (1) , i2c scl, spi mosi. 8 nc no connection. 9 power vss ground connection. 10 iohr i p1[0] issp data (1) , i2c sda, spi clk. 11 iohr i p1[2] 12 iohr i p1[4] optional external clock input (extclk). 13 iohr i p1[6] 14 input xres active high external reset with internal pull down. 15 io i p2[0] 16 ioh i p0[0] 17 ioh i p0[2] 18 ioh i p0[4] 19 ioh i p0[6] 20 power vdd supply voltage. 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input. 24 ioh i p0[1] integrating input. cp power vss center pad must be connected to ground. legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, data 2 , i2c sda, spi clk, p1[0] qfn (top view) ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, p1[2] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, clk 2 , i2c scl p0[1], ai vss ai, xout, p2[5] ai, xin, p2[3] note 3. the center pad (cp) on the qfn package must be connected to gr ound (vss) for best mechanical, thermal, and electrical perform ance. if not connected to ground, it should be electrically floated and not connected to any other signal. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 10 of 34 32-pin part pinout table 4. 32-pin qfn part pinout (2, 3) pin no. type name description figure 4. cy8c20446, cy8c20466 32-pin psoc device digital analog 1 ioh i p0[1] integrating input. 2 io i p2[7] 3 io i p2[5] crystal output (xout) 4 io i p2[3] crystal input (xin) 5 io i p2[1] 6 io i p3[3] 7 io i p3[1] 8 iohr i p1[7] i2c scl, spi ss. 9 iohr i p1[5] i2c sda, spi miso. 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk (1) , i2c scl, spi mosi. 12 power vss ground connection. 13 iohr i p1[0] issp data (1) , i2c sda., spi clk 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk). 16 iohr i p1[6] 17 input xres active high external reset with internal pull down. 18 io i p3[0] 19 io i p3[2] 20 io i p2[0] 21 io i p2[2] 22 io i p2[4] 23 io i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power vdd supply voltage. 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input. 32 power vss ground connection. cp power vss center pad must be connected to ground. legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, p0[1] ai, p2[7] ai, xout, p2[5] ai, xin, p2[3] ai, p2[1] ai, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai ai, p3[1] ai, i2c scl, spi ss, p1[7] p0[0], ai p2[6], ai p3[0], ai xres ai, i2c sda , sp i miso , p 1[5] ai, spi clk, p1[3] vss ai, p 1[2] ai, e xtclk , p 1[4] ai, p 1[6] p2[4], ai p2[2], ai p2[0], ai p3[2], ai p0 [5 ], ai ai, clk 4 , i2c scl, spi mosi, p1[1] ai, data 1 , i2c sda, spi clk, p1[0] [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 11 of 34 48-pin ssop part pinout table 5. 48-pin ssop part pinout (2) pin no. digital analog name description figure 5. cy8c20546, cy8c20 566-48-pin ssop psoc device 1 ioh io p0[7] 2 ioh io p0[5] 3 ioh io p0[3] 4 ioh io p0[1] 5 io io p2[7] 6 io io p2[5] xtal out 7 io io p2[3] xtal in 8 io io p2[1] 9 nc no connection 10 nc no connection 11 io io p4[3] 12 io io p4[1] 13 nc no connection 14 io io p3[7] 15 io io p3[5] 16 io io p3[3] 17 io io p3[1] 18 nc no connection 19 nc no connection 20 iohr io p1[7] i2c scl, spi ss 21 iohr io p1[5] i2c sda, spi miso 22 iohr io p1[3] spi clk 23 iohr io p1[1] tc clk (1) , i2c scl, spi mosi 24 vss ground pin 25 iohr io p1[0] tc data (1) , i2c sda, spi clk 26 iohr io p1[2] 27 iohr io p1[4] ext clk 28 iohr io p1[6] 29 nc no connection 30 nc no connection 31 nc no connection 32 nc no connection pin no. digital analog name description 33 nc no connection 41 io io p2[2] 34 nc no connection 42 io io p2[4] 35 xres active high external reset with internal pull down 43 io io p2[6] 36 io io p3[0] 44 ioh io p0[0] 37 io io p3[2] 45 ioh io p0[2] 38 io io p3[4] 46 ioh io p0[4] 39 io io p3[6] 47 ioh io p0[6] 40 io io p2[0] 48 power vdd power pin legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. ssop p0[7] vdd p0[5] p0[6] p0[3] p0[4] p0[1] p0[2] p2[7] p0[0] p2[5] p2[6] p2[3] p2[4] p2[1] p2[2] nc p2[0] nc p3[6] p4[3] p3[4] p4[1] p3[2] nc p3[0] p3[7] xres p3[5] nc p3[3] nc p3[1] nc nc nc nc nc p1[7] nc p1[5] p1[6] p1[3] p1[4] p1[1] p1[2] vss p1[0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 12 of 34 48-pin qfn part pinout table 6. 48-pin qfn part pinout (2, 3) pin no. digital analog name description figure 6. cy8c20666 48-pin qfn psoc device 1 nc no connection. 2 io i p2[7] 3 io i p2[5] crystal output (xout). 4 io i p2[3] crystal input (xin). 5 io i p2[1] 6 io i p4[3] 7 io ip4[1] 8 io i p3[7] 9 io i p3[5] 10 io i p3[3] 11 io i p3[1] 12 iohr i p1[7] i2c scl, spi ss. 13 iohr i p1[5] i2c sda, spi miso. 14 nc no connection. 15 nc no connection. 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk (1) , i2c scl, spi mosi. 18 power vss ground connection. 19 io d+ 20 io d- 21 power vdd supply voltage. 22 iohr i p1[0] issp data (1) , i2c sda, spi clk. 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk). 25 iohr i p1[6] 26 input xres active high external reset with internal pull down. 27 io i p3[0] 28 io ip3[2] 29 io ip3[4] pin no. digital analog name description 30 io ip3[6] 40 ioh i p0[6] 31 io i p4[0] 41 power vdd supply voltage. 32 io i p4[2] 42 nc no connection. 33 io i p2[0] 43 nc no connection. 34 io i p2[2] 44 ioh i p0[7] 35 io i p2[4] 45 ioh i p0[5] 36 io i p2[6] 46 ioh i p0[3] integrating input. 37 ioh i p0[0] 47 power vss ground connection. 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power vss center pad must be connected to ground. legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai, p4[3] ai, p4[1] ai, p3[7] ai, p3[5] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0 ], ai xres p1[6], ai p2[6], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spi clk, a i, p1[3] ai, clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai, data 1 , i2c sda, spi clk, p1[0] ai, p1[2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 13 of 34 48-pin qfn ocd part pinout the 48-pin qfn part is for the cy8c20066 on-chip debug (ocd) pso c device. note that this part is only used for in-circuit debugging. (4) table 7. 48-pin ocd qfn part pinout (2, 3) pin no. digital analog name description figure 7. cy8c20066 48-pin ocd psoc device 1 ocdoe ocd mode direction pin. 2 io i p2[7] 3 io i p2[5] crystal output (xout). 4 io i p2[3] crystal input (xin). 5 io i p2[1] 6 io i p4[3] 7 io ip4[1] 8 io i p3[7] 9 io i p3[5] 10 io i p3[3] 11 io i p3[1] 12 iohr i p1[7] i2c scl, spi ss. 13 iohr i p1[5] i2c sda, spi miso. 14 cclk ocd cpu clock output. 15 hclk ocd high speed clock output. 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk (1) , i2c scl, spi mosi. 18 power vss ground connection. 19 io d+ 20 io d- 21 power vdd supply voltage. 22 iohr i p1[0] issp data (1) , i2c sda, spi clk. 23 iohr i p1[2] pin no. digital analog name description 24 iohr i p1[4] optional external clock input (extclk). 37 ioh i p0[0] 25 iohr i p1[6] 38 ioh i p0[2] 26 input xres active high external reset with internal pull down. 39 ioh i p0[4] 27 io i p3[0] 40 ioh i p0[6] 28 io ip3[2] 41 power vdd supply voltage. 29 io ip3[4] 42 ocdo ocd even data io. 30 io ip3[6] 43 ocde ocd odd data output. 31 io i p4[0] 44 ioh i p0[7] 32 io i p4[2] 45 ioh i p0[5] 33 io i p2[0] 46 ioh i p0[3] integrating input. 34 io i p2[2] 47 power vss ground connection. 35 io i p2[4] 48 ioh i p0[1] 36 io i p2[6] cp power vss center pad must be connected to ground. legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 a i , p2[7] ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai, p3[7] ai, p3[5] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0], ai xres p1[6], ai p2[6], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, ai, p1[5] spi clk, a i, p1[3] ai, clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai, data 1 , i2c sda, spi clk, p1[0] ai, p1[2] ai, extclk, p1[4] p0[4], ai p0[1], ai ocdo e cclk hclk ocde ocdo note 4. this part is available in limited quantities for in-circuit debugging during prototype development. it is not available in pr oduction volumes. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 14 of 34 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c20x46/cy8c20x66 psoc device s. for the most up-to-date electrical specifications, confirm that you have t he most recent data sheet by going to the web at http://www.cyp ress.com/psoc . f i g u r e 8 . vo l ta g e v e r s u s c p u f r e q u e n c y f i g u r e 9 . i m o f r e q u e n c y tr i m o p t i o n s the following table lists the units of me asure that are used in this section. table 8. units of measure symbol unit of measure symbol unit of measure o c degree celsius ma milli-ampere db decibels ms milli-second ff femto farad mv milli-volts hz hertz na nanoampere kb 1024 bytes ns nanosecond kbit 1024 bits nv nanovolts khz kilohertz ? ohm ksps kilo samples per second pa picoampere k ? kilohm pf picofarad mhz megahertz pp peak-to-peak m ? megaohm ppm parts per million a microampere ps picosecond f microfarad sps samples per second h microhenry s sigma: one standard deviation s microsecond v volts w microwatts 5.5v 750 khz 24 mhz cpu frequency vdd voltage 5.5v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 1.71v 1.71v 3 mhz v a l i d o p e r a t in g r e g i o n slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10 [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 15 of 34 comparator user module electrical sp ecifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40c <= ta <= 85c, 1.71v <= vdd <= 5.5v. adc electrical specific ationsabsolute maximum table 9. comparator user module electrical specifications symbol description min typ max units conditions t comp comparator response time 70 100 ns 50 mv overdrive offset 2.5 30 mv current 20 80 a average dc current, 50 mv overdrive psrr supply voltage >2v 80 db power supply rejection ratio supply voltage <2v 40 db power supply rejection ratio input range 0 1.5 v table 10. adc user module electrical specifications symbol description min typ max units conditions input v in input voltage range vss 1.3 v this gives 72% of maximum code c in input capacitance 5 pf resolution 8 10 bits settings 8, 9, or 10 - 8-bit sample rate 23.4 375 ksps data clock set to 6 mhz. sample rate = 0.001/(2^resolution/data clock) - 10-bit sample rate 5.85 9 ksps data clock set to 6 mhz. sample rate = 0.001/(2^resolution/data clock) dc accuracy - dnl -1 +2 lsb for any configuration - inl -2 +2 lsb for any configuration - offset error 0 15 90 mv i adc operating current 275 350 a f clk data clock 2.25 12 mhz source is chip?s internal main oscil- lator. see device data sheet for accuracy. monotonicity not guaranteed. see dnl psrr power supply rejection ration - psrr (vdd>3.0v) 24 db - psrr (2.2 < vdd < 3.0) 30 db - psrr (2.0 < vdd < 2.2) 12 db - psrr (vdd < 2.0) 0 db gain error 1 5 %fsr for any resolution r in input resistance 1/ (500ff*data- clock) 1/ (400ff*data- clock) 1/ (300ff*data- clock) ? equivalent switched cap input resis- tance for 8-, 9-, or 10-bit resolution. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 16 of 34 ratings operating temperature dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 11. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperat ures reduces data retention time. recommended storage temperature is +25c 25c. extended duration storage temperatures above 85 o c degrades reliability. ?55 +25 +125 o c vdd supply voltage relative to vss ?0.5 ? +6.0 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss ?0.5 ? vdd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 200 ma table 12. operating temperature symbol description conditions min typ max units t a ambient temperature ?40 ? +85 o c t j operational die temperature the temperature rise from ambient to junction is package specific. see the table thermal impedances per package on page 28 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 o c table 13. dc chip-level specifications symbol description conditions min typ max units vdd supply voltage see the table dc por and lvd specifications on page 20 1.71 ? 5.5 v i dd24 supply current, imo = 24 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 24 mhz. capsense running at 12 mhz, no io sourcing current ? 2.88 4.0 ma i dd12 supply current, imo = 12 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 12 mhz. capsense running at 12 mhz, no io sourcing current ? 1.71 2.6 ma i dd6 supply current, imo = 6 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 6 mhz. capsense running at 6 mhz, no io sourcing current ? 1.16 1.8 ma i sb0 deep sleep current vdd = 3.0v, t a = 25 o c, io regulator turned off ? 0.1 ? a i sb1 standby current with por, lvd and sleep timer vdd = 3.0v, t a = 25 o c, io regulator turned off ? 1.07 1.5 a [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 17 of 34 dc general purpose io specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 5.5v an d ?40c t a 85c, 2.4v to 3.0v and ?40c t a 85c, or 1.71v to 2.4v and ?40c t a 85c, respectively. typical parameters apply to 5v and 3.3v at 25c and are for design guidance only. table 14. 3.0v to 5.5v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k ? v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 1 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 5 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh < 10 a, vdd > 3.1v, maximum of 4 ios all sourcing 5 ma 2.85 3.00 3.3 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5v out ioh = 2 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 1.60 1.80 2.1 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 25 ma, vdd > 3.3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin pin capacitance package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 18 of 34 table 15. 2.4v to 3.0v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k ? v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.2 ma, maximum of 10 ma source current in all ios vdd - 0.4 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.4v, maximum of 20 ma source current in all ios 1.50 1.80 2.1 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.4v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 10 ma , maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? 0.72 v v ih input high voltage 1.4 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf table 16. 1.71v to 2.4v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k ? v oh1 high output voltage port 2 or 3 pins ioh = 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.5 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 100 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v ol low output voltage iol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.4v v il input low voltage ? ? 0.3 x vdd v [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 19 of 34 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power comparat or specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v ih input high voltage 0.65 x vdd ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf table 16. 1.71v to 2.4v dc gpio specifications (continued) symbol description conditions min typ max units table 17.dc characteristics ? usb interface symbol description conditions min typ max units rusbi usb d+ pull up resistance with idle bus 0.900 - 1.575 k ? rusba usb d+ pull up resistance while receiving traffic 1.425 - 3.090 k ? vohusb static output high 2.8 - 3.6 v volusb static output low -0.3v vdi differential input sensitivity 0.2 - v vcm differential input common mode range 0.8 - 2.5 v vse single ended receiver threshold 0.8 - 2.0 v cin transceiver capacitance - 50 pf iio hi-z state data line leakage on d+ or d- line -10 - +10 a rps2 ps/2 pull up resistance 3 5 7 k ? rext external usb series resistor in series with each usb pin 21.78 22.0 22.22 ? table 18. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? 800 ? r gnd resistance of initialization switch to vss ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8v table 19. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to vdd 0.0 ? 1.8 v i lpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 20 of 34 dc por and lvd specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 20. dc por and lvd specifications symbol description conditions min typ max units v ppor0 v ppor1 v ppor2 v ppor3 vdd value for ppor trip porlev[1:0] = 00b, hpor = 0 porlev[1:0] = 00b, hpor = 1 porlev[1:0] = 01b, hpor = 1 porlev[1:0] = 10b, hpor = 1 vdd must be greater than or equal to 1.71v during startup, reset from the xres pin, or reset from watchdog. 1.61 ? 1.66 2.36 2.60 2.82 1.71 2.41 2.66 2.95 v v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 [5] 2.64 [6] 2.85 [7] 2.95 3.06 1.84 1.75 [8] 4.62 2.45 2.71 2.92 3.02 3.13 1.90 1.80 4.73 2.51 2.78 2.99 3.09 3.20 2.32 1.84 4.83 v v v v v v v v notes 5. always greater than 50 mv above v ppor1 voltage for falling supply. 6. always greater than 50 mv above v ppor2 voltage for falling supply. 7. always greater than 50 mv above v ppor3 voltage for falling supply. 8. always greater than 50 mv above v ppor0 voltage for falling supply. table 21. dc programming specifications symbol description conditions min typ max units vdd iwrite supply voltage for flash write operations 1.71 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc general purpose io specifications on page 17 ? ? v il v v ihp input high voltage during programming or verify see appropriate dc general purpose io specifications on page 17 table on pages 15 or 16 v ih ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify driving internal pull down resistor ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify driving internal pull down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? vss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc general purpose io specifications on page 17 table on page 16. for vdd > 3v use v oh4 in table 12 on page 16. v oh ? vdd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? cycles flash dr flash data retention following maximum flash write cycles; ambient temperature of 55c 10 20 ? years [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 21 of 34 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac general purpose io specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 22. ac chip-level specifications symbol description conditions min typ max units f max maximum operating frequency 24 ? ? mhz f cpu maximum processing frequency 24 ? ? mhz f 32k1 internal low speed oscillator frequency 19 32 50 khz f imo24 internal main oscillator frequency at 24 mhz setting 22.8 24 25.2 mhz f imo12 internal main oscillator frequency at 12 mhz setting 11.4 12 12.6 mhz f imo6 internal main oscillator frequency at 6 mhz setting 5.7 6.0 6.3 mhz dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width at power up after supply voltage is valid 1 ms t xrst2 external reset pulse width after power up applies after part has booted 10 s table 23. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71v cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 23 of 34 ac analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac programming specifications figure 11. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 27. ac analog mux bus specifications symbol description conditions min typ max units f sw switch rate maximum pin voltage when measuring switch rate is 1.8vp-p ??6.3mhz table 28. ac external clock specifications symbol description conditions min typ max units f oscext frequency 0.750 ?25.2mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 29. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? ? 18 ms t write flash block write time ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 < vdd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 vdd 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 vdd 3.0 ? ? 130 ns sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 24 of 34 ac spi specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. ac i 2 c specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. figure 12. definition for timing for fast/standard mode on the i 2 c bus table 30. ac spi specifications symbol description conditions min typ max units f spim maximum input clock frequency selection, master 2.4v cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 26 of 34 figure 15. 32-pin (5x5 x 0.6 mm) qfn figure 16. 48-pin (300 mil) ssop 001-42168 *b 51-85061 *c 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 27 of 34 figure 17. 48-pin (7x7 mm) qfn important note for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-13191 *c [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 28 of 34 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 32. thermal impedances per package package typical ja [10] 16 qfn 32.69 o c/w 24 qfn [11] 20.90 o c/w 32 qfn [11] 19.51 o c/w 48 ssop 69 o c/w 48 qfn [11] 17.68 o c/w table 33. solder reflow peak temperature package minimum peak temperature [12] maximum peak temperature 16 qfn 240 o c 260 o c 24 qfn 240 o c 260 o c 32 qfn 240 o c 260 o c 48 ssop 220 o c 260 o c 48 qfn 240 o c 260 o c notes 10. t j = t a + power x ja . 11. to achieve the thermal impedance specifi ed for the qfn package, the center thermal pad should be soldered to the pcb ground plane. 12. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 29 of 34 development tool selection this section presents the development tools available for all current psoc device families including the cy8c20x46/ cy8c20x66 family. software psoc designer? at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com under software. psoc express? as the newest addition to the psoc development software suite, psoc express is the first visual embedded system design tool that allows a user to create an entire psoc project and generate a schematic, bom, and data sheet without writing a single line of code. users work directly with application objects such as leds, switches, sensors, and fans. psoc express is available free of charge at http://www.cypress.com/psocexpress . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compat ible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com/psocpro- grammer . cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com/shop/ under product categories, click psoc? mixed signal arrays to view a current list of available items. development kits all development kits can be purc hased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyp ing and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specif ic memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples cy3210-expressdk psoc express development kit the cy3210-expressdk is for ad vanced prototyping and devel- opment with psoc express (may be used with ice-cube in- circuit emulator). it provides access to i 2 c buses, voltage reference, switches, upgradeabl e modules and more. the kit includes: psoc express software cd express development board 4 fan modules 2 proto modules miniprog in-system serial programmer minieval pcb evaluation board jumper wire kit usb 2.0 cable serial cable (db9) 110 ~ 240v power supply, euro-plug adapter 2 cy8c24423a-24pxi 28-pdip chip samples 2 cy8c27443-24pxi 28-pdip chip samples 2 cy8c29466-24pxi 28-pdip chip samples [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 30 of 34 evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluati on kit features a devel- opment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 31 of 34 accessories (emulation and programming) third-party tools several tools have been specially designed by the following third-party vendors to accompany psoc devices during development and production. specif ic details for each of these tools can be found at http://www.cypress.com under documentation >> evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, refer application note ? debugging - build a psoc emulator into your board - an2323 ? at http://www.cypress.com/ an2323 . table 34. emulation and programming accessories part number pin package flex-pod kit [13] foot kit [14] adapter [15] cy8c20246-24lkxi 16 qfn cy3250-20266qfn cy3250-16qfn-fk see note 15 cy8c20266-24lkxi 16 qfn cy3250-20266qfn cy3250-16qfn-fk see note 15 cy8c20346-24lqxi 24 qfn cy3250-20 366qfn cy3250-24qfn-fk see note 15 cy8c20366-24lqxi 24 qfn cy3250-20 366qfn cy3250-24qfn-fk see note 15 cy8c20446-24lqxi 32 qfn cy3250-20 466qfn cy3250-32qfn-fk see note 15 cy8c20466-24lqxi 32 qfn cy3250-20 466qfn cy3250-32qfn-fk see note 15 cy8c20546-24pvxi 48 ssop cy3250-20x66 cy3250-48ssop-fk see note 15 cy8c20566-24pvxi 48 ssop cy3250-20x66 cy3250-48ssop-fk see note 15 cy8c20666-24ltxi 48 qfn cy3250-20666qfn cy3250-48qfn-fk see note 15 notes 13. flex-pod kit includes a practice flex-pod an d a practice pcb, in addition to two flex-pods. 14. foot kit includes surface mount feet that can be soldered to the target pcb. 15. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 32 of 34 ordering information the following table lists the cy8c20x46 and cy8c20x66 psoc devices key package features and ordering codes. table 35. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital io pins analog inputs xres pin usb 16 pin (3x3 x 0.6 mm) qfn cy8c20246-24lkxi 16k 2048 1 13 13 [16] yes no 16 pin (3x3 x 0.6 mm) qfn (tape and reel) cy8c20246-24lkxit 16k 2048 1 13 13 [16] yes no 24 pin (4x4 x 0.6 mm) qfn cy8c20346-24lqxi 16k 2048 1 20 20 [16] yes no 24 pin (4x4 x 0.6 mm) qfn (tape and reel) cy8c20346-24lqxit 16k 2048 1 20 20 [16] yes no 32 pin (5x5 x 0.6 mm) qfn cy8c20446-24lqxi 16k 2048 1 28 28 [16] yes no 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20446-24lqxit 16k 2048 1 28 28 [16] yes no 48-pin ssop cy8c20546-24pvxi 16k 2048 1 36 36 [16] yes yes 48-pin ssop (tape and reel) cy8c20546-24pvxit 16k 2048 1 36 36 [16] yes yes 16 pin (3x3 x 0.6 mm) qfn cy8c20266-24lkxi 32k 2048 1 13 13 [16] yes no 16 pin (3x3 x 0.6 mm) qfn (tape and reel) cy8c20266-24lkxit 32k 2048 1 13 13 [16] yes no 24 pin (4x4 x 0.6 mm) qfn cy8c20366-24lqxi 32k 2048 1 20 20 [16] yes no 24 pin (4x4 x 0.6 mm) qfn (tape and reel) cy8c20366-24lqxit 32k 2048 1 20 20 [16] yes no 32 pin (5x5 x 0.6 mm) qfn cy8c20466-24lqxi 32k 2048 1 28 28 [16] yes no 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20466-24lqxit 32k 2048 1 28 28 [16] yes no 48-pin ssop cy8c20566-24pvxi 32k 2048 1 36 36 [16] yes yes 48-pin ssop (tape and reel) cy8c20566-24pvxit 32k 2048 1 36 36 [16] yes yes 48 pin (7x7 mm) qfn cy8c20666-24ltxi 32k 2048 1 36 36 [16] yes yes 48 pin (7x7 mm) qfn (tape and reel) cy8c20666-24ltxit 32k 2048 1 36 36 [16] yes yes 48 pin (7x7 mm) qfn (ocd) (4) cy8c20066-24ltxi 32k 2048 1 36 36 [16] yes yes notes 16. dual-function digital io pins also connect to the common analog mux. [+] feedback cy8c20x46, cy8c20x66 document number: 001-12696 rev. *c page 33 of 34 document history page document title: cy8c20x46 cy8c20x66 capsense tm applications document number: 001-12696 revision ecn origin of change submi ssion date description of change ** 766857 hmt see ecn new silicon and document (revision **). *a 1242866 hmt see ecn add features. update all applicab le sections. update specs. fix 24-pin qfn pinout moving pins inside. update package revisions. update and add to emulation and programming accessories table. *b 2174006 aesa see ecn added 48-pin ssop part pinout modified symbol r vdd to r gnd in table dc analog mux bus specification added footnote in table dc a nalog mux bus specification added 16k flash parts. upda ted notes, package diagrams and ordering information table. updated thermal impedance and solder reflow tables *c 2587518 tof/jasm/mnu/ hmt 10/13/08 converted from preliminary to final fixed broken links. updated data sheet template. added operating voltage ranges with usb adc resolution changed from 10-bit to 8-bit included adc specifications table included comparator specification table included voh7, voh8, voh9, voh10 specs flash data retention ? condition added to note input leakage spec changed to 1 a max gpio rise time for ports 0,1 and ports 2,3 made common ac programming specifications updated included ac programming cycle timing diagram ac spi specification updated the vih for 3.0 |
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